Integrated circuits are fabricated by the photolithographic projection of patterns formed on photomasks onto semiconductor wafers. In this case, a mask with the pattern corresponding to the circuit plane is generally used for each plane.
Large scale integrated circuits such as, for example, dynamic or nonvolatile memories and also logic chips are currently being fabricated with circuit elements whose width reaches down to 70 nm. In the example of the memory chips, this applies, for example, to the very densely and periodically arranged patterns of narrow word or bit lines and, if appropriate, the corresponding contact connections or memory trenches.
In this case, it can often happen that the corresponding large scale integrated structure patterns are arranged in a circuit plane jointly with the peripheral region that electrically connects the structure elements. Structure elements, for example, conductor tracks, of such peripheral regions are usually subject to relaxed requirements made of the structure width. Accordingly, dense, often periodic arrangements of structure elements and isolated or semi-isolated structure elements having larger dimensions are jointly arranged together in one pattern on the photomask to be used for the formation of the circuit plane.
It is known that during the lithographic projection, structure elements whose width is in the vicinity of the resolution limit of the respective exposure device are transferred into the image plane differently than nonperiodic structure elements having larger dimensions, due to optical imaging properties. This is due to the limited numerical aperture of the exposure device and to the individual exposure settings in the device. Given the presence of lens aberrations, for example, due to lens defects, the various imaging effects may be intensified and become visible in particular as line width variations or positional accuracy errors in the structure pattern portions.
FIG. 1 shows a simplified illustration of a detail from a circuit layout or a pattern 1 to be formed on a semiconductor wafer, which has both structure elements 14 arranged densely and periodically and structure elements 10, 12, 16 arranged in isolated or semi-isolated fashion. Areas depicted dark in the illustration represent elevated structure elements on the wafer, i.e. non-etched areas.
The structure element 10 corresponds, for example, to a contact hole that may be fabricated by irradiation of a corresponding opening on the mask into a photosensitive layer on the wafer (positive resist), a subsequent development and transfer into an underlying layer in an etching step.
FIG. 2 shows a solution approach for the above-mentioned problem of simultaneously imaging dense, periodic structure elements and isolated or semi-isolated structure elements. The solution approach is based on using halftone phase masks. The light-shading structure elements for forming the resist areas that are still unexposed on the wafer (areas depicted dark in FIG. 1) are not made opaque, but rather semitransparent on the mask. The light transmissivity is, for example, 6% transmission at a wavelength of 193 nm using oblique illumination.
The semitransparent structure elements 25, 26 are present both in a dense and periodic arrangement and in the form of isolated lines. On the mask relative to the wafer scale, the semitransparent structure elements have a longer length compared with the structure elements 14 to be formed on the wafer for compensating the line shortening effect. The isolated line 26 and the bright structures 28, 24 are assisted by so-called SRAF structures (subresolution assist features) 22, 27, which do not print onto the wafer, i.e., arise as actual resist structures on the wafer due to their width lying below the resolution limit of the exposure device.
For forming a mask bias, the structure elements 28, 24 embodied as gaps in the semitransparent region 20 are analogously made larger than the isolated or semi-isolated structure elements 10, 12 to be formed on the wafer, which is shown in the figures by the weakly dashed lines.
The use of the SRAF structures 22, 27 brings about an imaging of the isolated or semi-isolated structure elements as if these were situated in a dense environment of further structure elements. This reduces the difference between dense arrays and isolated structures during the optical projection. However, using halftone phase masks, the mask error enhancement factor (MEF) assumes particularly large values precisely, for example, in the cell array of memories having 70 nm width structure elements including lines and gaps. This factor represents the effect that, in the case of structures near the resolution limit, errors on the mask are transferred non-linearly into correspondingly formed widths on the wafer. The CD tolerance budget (CD: critical dimension) that is still available is generally exhausted early.
A further solution approach is to use transparent and phase-shifting structure elements in the region of the dense, highly integrated pattern portions. Oblique illumination is preferably to be set in this case. The structure formation on a wafer is effected based on the destructive interference at the image position of the phase edges of the phase-shifting structure elements with respect to the transparent, non-phase-shifting surface surrounding the structure element in each case. This procedure is also referred to as CPL technology (chromeless phase edge lithography). In this case, the structure elements are made so narrow that two adjacent phase edges lead to a line formation in the resist of a wafer. The lines are superimposed in their edges and thus merge to form a common line. Wider lines are formed with an opaque absorber, for example, chrome.
One example can be seen in FIG. 3, in which dense, periodic arrangements of structure elements 34 are etched into the surface 39 of a mask substrate as fully transparent, phase-shifting areas. The etching depth into the substrate, for example, quartz, is chosen to achieve a phase shift of 180° with respect to incident light in comparison with the surrounding surface of the mask substrate 39. SRAF structures 37 made from absorber or semitransparent halftone material may likewise be provided in order to improve the imaging behavior of semi-isolated lines. Wider lines may be enabled from a combination of absorbing structure elements 38 and of phase-shifting structure elements 381, 382. The imaging behavior of bright regions serving for the formation of the structure elements 10, 12 in the opaque environment 30 may be improved by RIM structure elements 32, 33, which yield a steeper intensity profile at the edges of the respective structure elements.
With this solution, that the process window for the regions embodied in chrome or other absorber materials is smaller than that for the comparable semitransparent regions of a halftone phase mask in accordance with FIG. 2. Furthermore, the above-mentioned RIM structure elements can be fabricated with the required accuracy only with very great difficulty. Further, due to the very narrow fully transparent, phase-shifting structure elements in the dense array of lines and gaps, a close-meshed coordinate grid is required for the mask writing and the volume of data for the mask writing process and also the mask inspection is therefore increased excessively. Finally, attention should also be drawn to an increased susceptibility to errors in the production, the measurement and in the error detection in the structure element arrangements.
An improvement of the solution approach shown in FIG. 3 is shown in the striplike structure pattern of FIG. 4. By alternate arrangements of chrome strips 43, 46 and fully transparent, phase-shifting structure elements 44, 45, the requirements made of the resolution during the mask writing process may be relaxed somewhat, while a high degree of dimensional accuracy is achieved for the structure elements to be formed on the wafer. However, the abovementioned disadvantages with regard to the problems of fabricating RIM structures, the reduced process window for the chrome regions and also the susceptibility to errors remain here, too.
Enlarging the process window for the imaging of a pattern from a mask onto a semiconductor wafer with very different degrees of periodicity and/or integrity is desirable. Furthermore, fabrication of structures in large scale integrated circuits with a width is smaller than previously possible with mask techniques used hereto, is desirable. Fabrication of masks with improved quality is desirable.